The present invention relates to a semiconductor memory device in which a redundant process for memory cells included therein is improved.
In a semiconductor memory device in which a plurality of memory cells are arranged in matrix form, if a defective memory cell exists in a row or a column of memory cells, the semiconductor memory device is provided with a redundant row or a redundant column in place of the row or column containing the defective cell.
For example, U.S. Pat. No. 4,250,570 which is a continuation of U.S. patent application Ser. No. 705,597 filed July 15, 1976 now abandoned, discloses a method for switching a row or a column containing a defective cell to a redundant row or a redundant column. Japanese Patent Kokai No. 51-93641, filed by the assignee of the subject application, Fujitsu Limited, discloses a semiconductor memory device in which a redundant row or column decoder for programming a defective address is provided, and Japanese Patent Kokai No. 52-27326 discloses a semiconductor memory device in which a read-only memory for storing a defective address is provided.
Further, U.S. patent application Ser. No. 258,572 filed June 1, 1972 and now U.S. Pat. No. 3,755,791, discloses a device in which a plurality of switching circuits, for every bit row or every bit column, is provided. However, in the switching circuits, the memory circuit for driving the memory cells requires many transistors and many electric sources, as well as a high-voltage source, so as to latch the information bits therein.